Chip packaging structure

ABSTRACT

A flip-chip package structure includes a flexible interconnection structure, at least one chip, a stiffener layer, and an isolating layer. The flexible interconnection structure having a plurality of bumps on a top surface, a plurality of contact terminals on a bottom surface, and an inner circuit connected to the bumps and the contact terminals. The chip and the stiffener layer are mounted on the top surface of the flexible interconnection structure, and the isolating layer is attached on the bottom surface. The isolating layer includes a plurality of openings that respectively expose the contact terminals of the flexible interconnection structure.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of a prior application Ser. No. 10/249,060, filed Mar. 13, 2003. The prior application Ser. No. 10/249,060 claims the priority benefit of Taiwan application serial no. 91132740, filed on Nov. 7, 2002.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to a chip packaging structure and a packaging process thereof. More particularly, the invention provides a chip packaging structure and a chip packaging process to increase the circuit layout density for high electrical performance.

2. Description of the Related Art

A flip chip interconnection structure usually consists of mounting a chip on a carrier substrate via a plurality of conductive bumps that electrically and mechanically connect the die pads of the chip to bump pads of the carrier substrate. Such an interconnection structure is particularly suitable for chip packages with a high pin count, and has the advantages of providing smaller surface areas and shorter electrical paths. Presently, two types of flip chip interconnection structures known in the art are a flip chip ball grid array (FC/BGA) package and a flip chip pin grid array (FC/PGA) package.

Referring to FIG. 1, a schematic view illustrates a structure of FC/BGA package known in the art. The FC/BGA package comprises a substrate 110, a chip 130, a plurality of conductive bumps 140, and a plurality of solder balls 150. The substrate 110 has a plurality of bump pads 116 a formed on the side of top surface 112, and a plurality of contact pads 116 b formed on an opposite bottom surface 114. First, the conductive bumps 140 electrically connect die pads 136 on the active surface 132 of the chip 130 through a bumping process. The conductive bumps 140 disposed on the chip 130 further electrically connect to the bump pads 116 a of the substrate 110. Meanwhile, the solder balls 150 are attached to the ball pads 116 b of the substrate for external connection.

An underfill compound 160 is further formed in the gap between the active surface 132 of the chip 130 and the top surface 112 of the substrate 110 to seal and protect the conductive bumps 140 by sharing thermal strains due to a thermal mismatch between the substrate 110 and the chip 130.

As the dimensional size of the chip package is reduced, the surface area of the chip and the pitch between the bump pads of the chip become increasingly smaller. In other words, the density of the die pads becomes higher. To adequately accommodate the density of the die pads of the chip, the substrate also has to be provided with a high density of bump pads and a finer circuit layout.

The known FC/BGA or FC/PGA package currently uses a substrate made of ceramic or organic based materials. It should be remarked that the organic substrate is more common. Due to a substantial thermal expansion of the organic material, the trace width and trace pitch currently obtainable inside the substrate are limited to be above 25 μm. The bumps disposed on the chip also have a height at lest 100 μm. Furthermore, due to the nature of its material, a maximal size of the blank (before cutting) of the organic substrate is limited to 610 mm×610 mm. The above technical limitations of the prior art are not satisfactory in view of current demands.

SUMMARY OF THE INVENTION

An aspect of the invention is therefore to provide a chip packaging structure that increases the circuit layout density of the multi-layer interconnection structure for higher electrical performance.

Another aspect of the invention is to provide chip packaging structure that reduces the production cost.

To accomplish the above and other objectives, a chip packaging structure of the invention comprises a multi-layered interconnection structure, a chip, a stiffener layer, and an isolating layer. The multi-layered interconnection structure has a plurality of bumps on a top surface and a plurality of contact terminals on a bottom surface, and internally includes inner electrical circuits connected to the bumps and the contact terminals. The multi-layered interconnection structure is a flexible structure which is built-up on a base substrate. The chip is mounted on the top surface of the multi-layered interconnection structure in a manner to be electrically connected to the bumps according to a flip chip type. The stiffener layer has a cavity, and is attached on the top surface of the multi-layered interconnection structure with the cavity receiving the chip therein. The isolating layer is attached on the bottom surface of the multi-layered interconnection structure, and includes a plurality of openings that respectively expose a plurality of contact terminals on the bottom surface of the multi-layered interconnection structure.

According to an embodiment of the invention, the stiffener layer comprises a stiffener substrate and a heat sink. The stiffener substrate includes a hole, and the heat sink is attached on the stiffener substrate in a manner to cover the hole.

According to another embodiment of the invention, the stiffener layer is a heat sink.

According to a preferred embodiment of the invention, the base substrate is made of quartz or glass or ceramics, and a fabrication process of a thin film transistor-liquid crystal display (TFT-LCD) panel or a fabrication process of an integrated circuit (IC) is used to form the multi-layered interconnection structure over the base substrate. The obtained multi-layered interconnection structure thereby has bump pads and inner circuit layout with a higher density.

It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

FIG. 1 is a schematic view of a FC/BGA packaging structure known in the prior art;

FIG. 2A through FIG. 2K are schematic views of a chip packaging process according to the first embodiment of the invention;

FIG. 3A through FIG. 3D are schematic views of a chip packaging process according to the second embodiment of the invention;

FIG. 4 is a schematic view of a chip packaging structure according to the third embodiment of the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The following detailed description of the embodiments and examples of the present invention with reference to the accompanying drawings is only illustrative and not limiting. Furthermore, wherever possible in the description, the same reference symbols will refer to similar elements and parts unless otherwise illustrated in the drawings.

Reference now is made to FIG. 2A through FIG. 2K to describe a chip packaging process according to an embodiment of the invention. In FIG. 2A and FIG. 2B, an isolating layer 204 is formed on a base substrate 202. The base substrate 202 is preferably made of quartz or glass or ceramics, and preferably has a highly planar surface. The isolating layer 204 is made of, for example, polymer, polyester, polyimide (PI), epoxy resin, or benzocyclobutene (BCB). The isolating layer 204 may be adhered on the substrate 202 via film attachment or coating.

Referring to FIG. 2C, a multi-layered interconnection structure 206 is formed on the isolating layer 204. The multi-layered interconnection structure 206 principally includes a plurality of conductive traces 208, at least a dielectric layer 210, and a plurality of interconnection vias 212 that electrically connect the conductive traces 208 through the dielectric layer 210, thereby forming inner electrical circuits. The conductive traces 208 are made of, for example, copper, aluminum (most commonly used), or other adequate conductive metallic alloys. The dielectric layer 210 is made of, for example, silicon nitride and/or silicon oxide. Because the multi-layered interconnection structure 206 formed on a base substrate 202, the present invention provides a thin multi-layered interconnection structure 206 regardless of the rigid of the multi-layered interconnection structure 206. In other words, the multi-layered interconnection structure 206 is a flexible and thin structure for the interconnections of a chip.

According to a preferred embodiment, a processing technique used in the fabrication of thin film transistor/liquid crystal display (TFT-LCD) panels is implemented to form the multi-layered interconnection structure. The obtained width and pitch of both the conductive traces 208 within the structure 206 are between about 1 μm and 50 μm and, more particularly, in the order of microns (even smaller than 1 μm). Therefore, compared with the usually known organic substrate 110 of FIG. 1, the multi-layered interconnection structure 206 provides a higher density of the bump pads and a finer circuit layout. Furthermore, passive components (not shown) may be further incorporated inside the structure 206 (connected to the conductive traces). Passive components such as capacitors, resistor, or inductors may be formed via, for example, a specific routing design of the conductive traces within the structure 206.

Referring to FIG. 2D, a chip 214 is flip-chip mounted on the structure 206, and is thereby electrically connected to its inner electrical circuits. For this purpose, the conductive traces 208 typically form a plurality of bump pads 208 a on a top surface 206 a of the structure 206. The bump is made of a soldering material or selected from the group consisting of gold(Au), copper(Cu), nickel(Ni), and stannum(Sn). For example, the bump is made of Au, Cu, Au/Ni, or Au/Sn. The underfill material may be filled between the chip 214 and the multi-layered interconnection structure 206 if the underfill material is disposed on the top surface 206 a of the multi-layered interconnection structure 206 before mounting the chip 214. Furthermore, the bump 218 formed on the multi-layered interconnection layer 206 has a height not larger than 50 μm. In the process of mounting the chip, the die pad 216 on an active surface 214 a of the chip 214 are respectively jointed to a bump 218. More particularly, a soldering material exists between the die pad 216 and the bump 218 for the joint therebetween through a thermal pressing process.

Referring to FIG. 2E, a stiffener substrate 220 is further attached on the structure 206 to reinforce the mechanical strength and establish further electrical connections. The attachment of the stiffener substrate 220 may be achieved through, for example, an adhesive layer 230 formed on the top surface 206 a of the structure 206. For economical cost consideration, the stiffener substrate 220 is, for example, an organic chip carrier substrate that could be a two-layered substrate and be incorporated passive components either on its surface or embedded inside. The stiffener substrate 220 includes at least one hole 222, for example formed by punching, in which is received the chip 214.

In the illustrated embodiment of FIG. 2E, the stiffener substrate 220, for example, includes an insulating core 224, two conductive layers 226 formed on two opposite surfaces of the core 224, and a plurality of plated through holes (PTH) 228 electrically connecting the conductive layers 226 through the core 224. The adhesive layer 230 further internally includes a plurality of conductive vias 232 that electrically connect the conductive layers 226 of the stiffener substrate 220 to the conductive traces 208 of the structure 206. Therefore, the inner routing space is increased. The conductive vias 232 may be constituted by, for example, forming openings through the adhesive layer 230 and filling these openings with a conductive paste. Furthermore, the stiffener substrate 220 could include at least one passive component arranged inside the substrate 220 or on the surface of the substrate 220.

Referring to FIG. 2F, a sealing compound 234 is filled between the chip 214 and the structure 206, and in the gap between the chip 214 and the sidewall of the hole 222 to prevent the presence of gaseous voids that may undesirably produce a “popcorn” effect. It should be noticed that the portion of sealing compound 234 between the chip 214 and the structure 206 may be previously formed at the step illustrated in FIG. 2D by underfill to share thermal strains.

Referring to FIG. 2G, a heat sink 236 may be further attached on the chip 214 and the stiffener substrate 220. The heat sink 236 is made of, for example, copper, aluminum, or other adequate metallic alloys, and is attached via an adhesive layer 238. The heat sink 236 with the stiffener substrate 220 further reinforce the mechanical strength of the entire structure, and promote heat dissipation by convection through its surface to external environment.

Next referring to FIG. 2H and FIG. 21, the base substrate 202 is removed to expose the isolating layer 204. To facilitate this operation, a light may be radiated through the base substrate 202 to the isolating layer 204 to reduce the adhesion between both layers. The radiated light may be an ultra-violet light or a laser beam. Alternatively, heating may be used to reduce the adhesion between both layers 202, 204. To prevent the damage of the electrical circuitry (including that of the chip 214) located over the isolating layer 204 due to light irradiation, the isolating layer may be made of a composite structure, for example including a light barrier layer sandwiched between two dielectric layers (not shown). The light barrier layer stops the radiated light, which therefore prevents its reaching and damaging the electrical circuitry above the isolating layer 204. Once having been removed, the base substrate 202 may be economically reused.

Next referring to FIG. 2J, a plurality of openings 204 a are formed through the isolating layer 204 to respectively expose a plurality of contact terminals 208 b defined from the conductive layer 208 of the structure 206. A photo via process, plasma etching or laser ablation may be adequate to form the openings 204 a.

Next referring to FIG. 2K, a plurality of external connection members 240 are respectively formed on the contact terminals 208 b. The connection members 240 may be, for example, solder balls or connection pins. Thereafter, a singulation process is performed to obtain an individual chip package 200. Alternatively, the singulation process may be performed before the connection members 240 are formed at the stage shown in FIG. 2J.

The connection members 240 are preferably distributed in grid array on the bottom surface 206 b of the structure 206, so that the formed chip package is either a ball grid array or pin grid array package depending on whether the connection members 240 are solder balls or connection pins.

As described above, the chip packaging process of the invention therefore economically uses a stiffener substrate that, associated with a heat sink, reinforce the mechanical strength of the package structure and further promote heat dissipation through the heat sink. Alternatively, a single heat sink provided with a cavity may be substituted for the above association of a stiffener substrate and a heat sink as described in the following second embodiment of the invention.

Reference now is made to FIG. 3A through FIG. 3D to describe a chip packaging process according to a second embodiment of the invention. It should be noticed that only the processing steps particular to this second embodiment are illustrated, and the description of the processing steps common to the first and second embodiments are omitted.

As illustrated in FIG. 3A, an isolating layer 304 and a multi-layered interconnection structure 306 are sequentially formed on a base substrate 302, and a chip 314 is flip-chip mounted on the top surface 306 a of the structure 306, similar to the first embodiment. A heat sink 342, having a cavity 344, is attached on the top surface 306 a via an adhesive layer 330, with the cavity 344 facing down to receive the chip 314 therein. The heat sink 342 is preferably made of a material having good thermal conduction such as copper or aluminum. The adhesive layer 330 includes a plurality of conductive vias 332 that connect the conductive traces inside the structure 306 to the heat sink 342. If the heat sink 342 is electrically conductive, a power reference or ground reference can be thereby provided.

A sealing compound 346 is filled in the gaps between the chip 314 and the structure 306 and the gaps between the chip 314 and the inner sides of the cavity 344 to prevent a popcorn effect.

Referring to FIG. 3B and FIG. 3C, the base substrate 302 then is removed to expose the isolating layer 304 according to a manner similar to the first embodiment. Openings 304 a then are formed through the isolating layer 304 to expose contact terminals 308 b on the bottom surface 306 b of the structure 306, on which external connection members 340 are formed.

Referring to FIG. 3D, connection members 340 are subsequently attached to the contact terminals 308 b, similar to the previous embodiment.

The above embodiments describe a packaging structure that principally comprises a single chip. However, more than one chip may be also similarly included in the packaging structure as described below.

Referring to FIG. 4, a schematic view illustrates a packaging structure according to a third embodiment of the invention. As illustrated, a chip module 414 is packaged in the packaging structure. The chip module 414 includes a plurality of chips 414 a, 414 b that are flip chip mounted on the multi-layered interconnection structure 406 and electrically connected through its inner circuit. The chips 414 a, 414 b are thereby interconnected through the inner circuits of the multi-layered interconnection structure 406, and can therefore form a multi-chip module (MCM) or a system in package (SIP).

As described above, the invention therefore provides a chip packaging comprising a flexible interconnection structure, at least one chip, a stiffener layer and an isolating layer. The flexible interconnection structure having a plurality of bumps on a top surface, a plurality of contact terminals on a bottom surface, and the inner electrical circuits electrically connected to the bumps and the contact terminals. The chip is connected to the bumps of the flexible interconnection structure by a flip-chip type.

The chip package is fabricated through the following steps: providing the base substrate; forming the isolating layer on the base substrate; forming the multi-layered interconnection structure on the isolating layer; mounting the chip on the top surface of the multi-layered interconnection structure; attaching the stiffener layer on the top surface of the multi-layered interconnection structure; removing the base substrate; and forming the openings of the isolating layer. The openings of the isolating layer could be formed after removing the base substrate or before forming the multi-layered interconnection structure on the isolating layer. The advantages implemented in the invention are:

-   -   1. The flexible interconnection structure with a high density of         bump pads and a finer inner circuit layout (trace pitch and         trace width.     -   2. The specific flexible interconnection structure used in the         invention can advantageously accommodate one or more chips         having a high density of bump pads.     -   3. The flexible interconnection structure allows an easier         control of the electrical impedance of the conductive traces.     -   4. The contact terminals on the bottom surface of the flexible         interconnection structure are the solder balls or the conductive         pins.     -   5. Furthermore, the base substrate can have a larger surface         area, typically larger than 610 mm×610 mm. More chip packages         can be therefore fabricated from a single base substrate, which         decreases the fabrication cost.

It should be apparent to those skilled in the art that other structures that are obtained from various modifications and variations of different parts of the above-described structures of the invention would be possible without departing from the scope and spirit of the invention as illustrated herein. Therefore, the above description of embodiments and examples only illustrates specific ways of making and performing the invention that, consequently, should cover variations and modifications thereof, provided they fall within the inventive concepts as defined in the following claims. 

1. A chip package structure, comprising: a flexible interconnection structure, having a top surface and an opposite bottom surface, the flexible interconnection structure including inner electrical circuits that are electrically connected to a plurality of bumps on the top surface of the flexible interconnection structure and a plurality of contact terminals located on the bottom surface of the flexible interconnection structure, wherein the bumps have a height not larger than 50 μm; at least one chip, mounted on the top surface of the flexible interconnection structure and electrically connected to the bumps; a stiffener layer, attached on the top surface of the flexible interconnection structure; and an isolating layer, attached to the bottom surface of the flexible interconnection structure, the isolating layer including a plurality of openings that respectively expose the contact terminals on the bottom surface of the multilayered interconnection structure, wherein the isolating layer and the flexible interconnection structure are sequentially formed on a base substrate before the chip and the stiffener layer are attached on the top surface of the flexible interconnection structure.
 2. The chip package structure of claim 1, wherein the chip is mounted on the top surface of the flexible interconnection structure by a flip-chip type.
 3. The chip package structure of claim 1, wherein the stiffener layer includes a stiffener substrate with a hole and a heat sink attached on the stiffener substrate in a manner to cover the hole, wherein the structure of the stiffener substrate and the heat sink results in the cavity of the stiffener layer.
 4. The chip package structure of claim 3, wherein the stiffener substrate includes inner circuits that are electrically connected to the inner electrical circuits of the flexible interconnection structure.
 5. The chip package structure of claim 3, wherein the stiffener substrate further includes at least one passive component that is embedded therein.
 6. The chip package structure of claim 3, wherein the stiffener substrate further includes at least one passive component that is mounted on a surface thereof.
 7. The chip package structure of claim 1, wherein the stiffener layer has a cavity that receives the chip therein.
 8. The chip package structure of claim 7, wherein the stiffener layer is a heat sink.
 9. The chip package structure of claim 1, further comprising at least a passive component formed inside the flexible interconnection structure and electrically connected to the inner electrical circuits.
 10. The chip package structure of claim 1, wherein the bumps are selected from the group consisting of Au, Cu, Ni and Sn.
 11. The chip package structure of claim 10 further comprises a soldering material disposed between the bumps of the flexible interconnection structure and the chip, such that the bumps of the flexible interconnection structure and the chip are electrically connected through a thermal-pressing process.
 12. The chip package structure of claim 1, wherein the bumps are made of a soldering material.
 13. The chip package structure of claim 1, wherein the base substrate is selected from one of the glass, quartz and ceramics.
 14. The chip package structure of claim 1, wherein the contact terminals are a plurality of solder balls.
 15. The chip package structure of claim 1, wherein the contact terminals are a plurality of conductive pins.
 16. The chip package structure of claim 1, wherein the flexible interconnection structure is formed through a build-up process on the base substrate.
 17. The chip package structure of claim 1, wherein the base substrate is removed after the chip and the stiffener layer are attached on the top surface of the flexible interconnection structure.
 18. A method for fabricating the chip package structure of claim 17, comprising the following steps: providing the base substrate; forming the isolating layer on the base substrate; forming the multi-layered interconnection structure on the isolating layer; mounting the chip on the top surface of the multi-layered interconnection structure; attaching the stiffener layer on the top surface of the multi-layered interconnection structure; removing the base substrate; and forming the openings of the isolating layer.
 19. The method claim 18, wherein the openings of the isolating layer are formed after removing the base substrate.
 20. The method of claim 18, wherein the openings of the isolating layer are formed before forming the multi-layered interconnection structure on the isolating layer. 